An Asynchronous Self-Routing Adaptive Reconfigurable FPGA
نویسندگان
چکیده
Architecture: We investigate an architecture with all memory information on one side of the array, leaving computation on the other to achieve speed and compactness. The array consists of a column of CLB’s, interconnected by a Self-Routing Network. The network (Omega) routes data packets on the basis of their content. An 32 CLB array is 1.8Kx15K sq.lambda. With asynchronous signalling, logic-blocks are reconfigured as soon as their operands are ready. The delay across one stage of the network is 250ps(2lambda=.25um), with no need of a over GHz clock synchronizing the stages across the system. Low-power adaptive circuits were designed to maximize wire bandwidth. In this way, both logic-blocks and wiring resources are re-used over time reaching optimal hardware exploitation and task independence.
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